1. Field of the Invention
The invention relates to a charge pump circuit, and more particularly, to a charge pump circuit suitable for a low-voltage process and having a high pumping gain.
2. Description of the Prior Art
When using the general volatile memory devices, such as dynamic random access memory (DRAM) or static random access memory (SRAM), the stored data will be removed after turning the power off. If we want to keep the data after turning the power off, we should use the non-volatile memory devices, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory (Flash).
The EEPROM or Flash needs a charge pump circuit to provide a voltage higher than the integrated circuit voltage source to perform the program or erase procedure. The charge pump circuit can provide not only the high voltage required for operation of the memory devices but also can provide the high voltage for other purposes.
FIG. 1 shows a common charge pump circuit (called Dickson C.P.), which is a 4-stage charge pump. The charge pump circuit provides memory devices with high voltage by controlling a series of connected NMOS transistors and capacitors to boost the voltage source (VDD) stage by stage. But the threshold voltage (Vt) of a diode-connected MOSFET is increased due to the body effect while voltage of each pumping node is boosted, that may cause lowering of efficiency of the charge pump. The aggravation of the charge pump has a negative influence on the low-voltage source, and may cause the invalidity of the charge pump circuit for memory devices using low-voltage source.
For improving the pumping gain, another charge pump circuit (called J.-T C.P.) is developed. The charge pump circuit provides a method to transfer charges while the forward bias of the diode-connected MOSFET is lower than the threshold voltage. As shown in FIG. 2(a), a charge transfer circuit (CTS) is added into the charge pump circuit, and the MOSFET switch is timely opened or closed to be a charge transfer circuit to transfer charges. The pumping gain of the charge pump is improved to VG=ΔV=VDD by means of the charge transfer circuits, and if the parasitic capacitance of each pumping node is ignored, the maximum voltage difference between each pumping stage will be Vd(max)=VDD+VG=2VDD. Please also refer to FIG. 2(b). The voltage difference between node 1 and node 2 is marked as V12, which has a maximum value 2VDD between time periods T1 and T3, and this situation also happens on simultaneous V34 and V23 between time periods T2 and T4. If the voltage source is a typical voltage source used in manufacturing process, such as 1.8V used in the 0.18 μm process of the 40 Å thickness gate oxide layer, most MOSFETS in the circuit will exceed the bearable voltage of the gate oxide layer (2*1.8=3.6V) that leads to the avalanche of the gate oxide layer and the failure of the device.
The conventional charge pump circuit has an exceeding high voltage on the gate oxide layer in the low-voltage manufacture process and the pumping gain of the conventional charge pump circuit is not high enough, so the present invention provides a charge pump circuit suitable for a low-voltage process and having a high pumping gain to overcome the disadvantages.